1. Field of the Invention
The present invention relates to a display device and a method of manufacturing the display device. In particular, the invention relates to a display device including a thin film transistor having a crystalline silicon layer as a channel active layer.
2. Description of Related Art
In recent years, there have been developed active matrix display devices where plural signal lines and plural scanning lines are arranged in matrix, and a thin film transistor (TFT) as a switching element is formed in a pixel area surrounded by the signal lines and the scanning lines. The active matrix display devices excel passive matrix display devices in image quality and thus prevail over other organic EL display devices and liquid crystal display devices. A LTPS TFT including a channel active layer made of low temperature polysilicon (LTPS) has high electron mobility. Performances of the active matrix display devices have been dramatically improved using the LTPS TFT.
For example, the LTPS TFT is applied to a peripheral circuit portion for driving a switching element. If the LTPS TFT is used for peripheral circuits of the display device, it is possible to reduce the number of ICs and IC-equipped substrates for use in devices. As a result, the display device configuration can be simplified and a high-reliability display device with a narrow frame is realized.
Further, in the liquid crystal display devices, if the LTPS TFT is used as a switching element for each pixel, it is possible to reduce not only a capacitance thereof but an area of a storage capacitor connected to the drain side. Therefore, a liquid crystal display device (LCD) of high resolution and high aperture ratio can be attained. Thus, the LTPS TFT plays a leading role in displaying high-resolution images such as QVGA (240×320 pixels) or VGA (480×640 pixels) with a liquid crystal display device with a small panel like a cell phone display panel. In this way, the LTPS TFT is more advantageous than an amorphous silicon (a-Si) TFT in terms of performance.
However, existing LTPS TFTs have problems of many manufacturing steps and low productivity compared with the a-Si TFT. Here, a difference in manufacturing process between the a-Si TFT and the LTPS TFT is described in detail based on the LCD.
As a result of comparing a manufacturing process for an a-Si TFT LCD with that for an LTPS TFT LCD array, the number of patterning steps is 5 for the a-Si TFT LCD but is 8 for the LTPS TFT. A breakdown of the additional three patterning steps necessary for the LTPS TFT is as follows:    (1) a selective doping step for forming a C/MOS structure (unnecessary if the TFT structure is one-conductivity type: N type or P type)    (2) a doping step for reducing a resistance of a lower-electrode-formation polysilicon layer of a storage capacitor    (3) a step of forming contact holes for source/drain lines inclusive of a signal line.
The difference of 3 patterning steps largely influences productivity, and a production cost exceeds a low component cost for ICs and IC-equipped substrates, which is an advantage of the LTPS TFT LCD. As a result, the display device using the LTPS TFT is inferior in product competitiveness to the a-Si TFT. This problem is applicable to active matrix display devices other than the LCD, such as an active matrix organic EL display device (AMOLED).
To that end, Japanese Unexamined Patent Application Publication Nos. 6-194689 and 2003-131260 (Miyasaka) disclose a technique of forming a source/drain line below a gate insulating layer to directly contact a source/drain region in a silicon layer with the source/drain line to use the line as a lower electrode of a storage capacitor. As a result, it is possible to skip the aforementioned two steps: (2) doping step for reducing a resistance of a lower-electrode-formation polysilicon layer of a storage capacitor and (3) step of forming contact holes for source/drain lines. For example, the technique of Miyasaka directly connects the source/drain line with the silicon layer to reduce the number of steps.
The TFT structure of Miyasaka has a silicon layer formed on a metal line, and many defects occur in the LTPS TFT. The LTPS is generally obtained by forming an a-Si layer and locally-heating the a-Si layer surface with a laser to fuse and crystallize the a-Si layer. Under heating at high temperature, metal contamination proceeds from the base metal line to a silicon layer. Hence, a TFT junction in the silicon layer is deteriorated to increase a leak current.
Further, in general, an a-Si layer is heated by moving a laser beam which has linear spot in a laser annealing step. A crystal structure of a silicon layer differs between a case where a direction in which a region is heated with the linear spot of laser beam is vertical to a direction of a source/drain region having a metal line at the end portion and the case where the two directions are parallel to each other. A difference of the crystal structure causes a difference in TFT characteristics. If the TFT structure of Miyasaka is applied to the LTPS TFT, the TFT characteristics vary, and a current leaks and its reliability lowers due to the defects.